Fast and Low-Error Prediction of Logic Gate Cell Characterization

Citation: Jacinto, G. L. (2023). "Fast and Low-Error Prediction of Logic Gate Cell Characterization." IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS).
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This work proposes a machine learning approach for cell characterization of logic gates. Traditional electrical simulation-based characterization faces challenges related to foundry secrecy and runtime. The proposed framework addresses these challenges by utilizing ML models to estimate power consumption and propagation times. The experiments demonstrate the potential of the framework to predict different logic gate functions in different technology models, showing the feature extraction differences for bulk CMOS and FinFET devices. Results demonstrate the effectiveness of the Decision Tree algorithm in fast and accurately predicting cell behavior, with inference times almost a thousand times faster than the traditional electrical simulation and coefficient of determination superior to 95%.